Two dimensional (2D) NAND flash memory uses floating gate transistors organised into a cell which can be programmed to store a varying level of electrical charge. The number of different voltage levels, q, to which a cell can be programmed allows representation of log2 q binary bits per cell. Many such cells can be grouped into a logical page and pages grouped into logical blocks. A page is the smallest addressable unit for reading and writing data, whilst a block is the smallest erasable unit.
Cells can be connected in series to form a string, with a selection transistor placed at each end. Groups of strings tend to share common control lines for the selection transistors; one called a bit line and the other called a source line. Word lines are formed by connecting together the control gate of the floating gate transistors.
Each cell can be set into one of q logical states in Q={s0, . . . , sq-1}, where s0 corresponds to the erased state (no charge) while the remaining states represent the programmed states with a different charge for each. The cases with q=2, 4, 8 are also known as single, multi and triple-level cell (SLC, MLC and TLC) technologies respectively. The logical state of a cell is mapped into a voltage level reflecting the charge stored in its floating gate, i.e. s0 reflects the lowest voltage while sq-1 reflects the highest voltage. Without loss of generality, it can be assumed that the states themselves are the voltages.
Each cell can be treated as an individual storage medium. Since each cell can be in one of q states, each log2 q bits can be stored into a cell by setting its voltage to the corresponding value. For example, in the case of q=4, have 11→s0, 10→s1, 00→s2 and 01→s3.
Once programmed, the voltage of a cell can be perturbed from a number of processes. The major sources of noise are random telegraph noise (RTN) and charge leakage, which are the result of physical deterioration of the floating gate transistor.
In addition to noise, cells with close proximity to a cell being programmed with a high voltage will suffer from parasitic capacitance coupling. This will make the voltage shift of a programmed cell induce a voltage shift in neighbouring cells. This effect is referred to as cell to cell interference (CCI). Cell to cell interference becomes stronger as the density of the device increases.
Furthermore, repeated programming and erasing of memory cells can lead to the cells wearing over time. This means that flash memory tends to have a finite number of program-erase cycles before data can no longer be reliably retrieved.
There is therefore a need for providing an improved method of storing data which can improve device reliability and reduce stress on individual cells.